Optimal Gate Sizing with Multiple Vt Assignment using Generalized Lagrangian Relaxation
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چکیده
Simultaneous gate sizing with multiple Vt assignment for optimal delay and power is a complicated task in modern custom designs. In this work, we make the key contribution of a novel gate-sizing and multi-Vt assignment technique based on generalized Lagrangian Relaxation. Experimental results show that our technique has linear runtime and memory usage, and can optimally tune circuits with over 15,000 variables and 8,000 constraints in under 8 minutes (250x faster than state-of-the-art optimization solvers).
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